1. Field of the Invention
The invention relates to a computer system, more particularly to one having an integrated core and graphic controller device capable of accessing memory data simultaneously from a system memory pool and a separate stand-alone frame buffer memory pool.
2. Description of the Related Art
Referring to FIG. 1, a conventional personal computer system 1 is shown to comprise a central processing unit (CPU) 10, a host bus 11 connected to the CPU 10, a core logic 12 connected to the host bus 11, a memory bus 13 connected to the core logic 12, a system memory pool 14 connected to the memory bus 13, an input/output (I/O) bus 15 connected to the core logic 12, at least one peripheral device 16 connected to the I/O bus 15, an Advanced Graphic Port (AGP) bus 17 connected to the core logic 12, a stand-alone graphic accelerator (VGA) card 18 connected to the AGP bus 17, and a monitor 19 connected to the VGA card 18. The VGA card 18 includes a VGA chip 181, a local frame buffer 182 formed from dynamic memory, and a flash memory 183 for VGA BIOS.
Referring to FIG. 2, it has been proposed heretofore in another conventional personal computer system 2 to discard the stand-alone VGA card 18, and mount the VGA chip 181 and the local frame buffer 182 directly on the system board (not shown) to reduce costs and simplify manufacture of the system board.
Due to continued growth in multimedia applications, VGA processing needs more memory bandwidth and faster computing capability for larger data access to maintain optimum display quality and performance. Since the traditional VGA 64-bit frame buffer memory data (MD) bus cannot meet the performance target, a 128-bit frame buffer MD architecture has been proposed. The 128-bit MD bus lines allow the VGA chip to access 128-bit data per memory transaction to result in doubling of the performance as compared with the traditional 64-bit MD scheme. FIG. 3 illustrates a proposed computer system 3 having a VGA chip 381 connected to a local frame buffer 383 via a 128-bit frame buffer MD bus 382. Although VGA performance is improved, too many memory pins are needed to make the proposed computer system 3 work. In a recommended memory signal layout on a system board, the layout trace width is about 6 mil, the spacing between traces is about 6 mil, the via hole diameter is about 12 mil, and the spacing between via is about 50 mil. Thus, for the proposed computer system 3, at least 6xc3x9764xc3x972=768 mil is needed for the additional 64-bit MD signal lines, and more than 400 mil is spent for additional memory address and control signal lines. Therefore, the system board has to be enlarged to obtain sufficient trace space and for reasonable trace layout routing. This violates the trend toward making the system board more compact and more cost effective. In addition, the 128-bit MD bus lines will dramatically complicate the chipset-to-memory layout and will degrade the signal quality during run time. If BGA layout concerns are to be included, there is a need to reserve more space on the system board for extra signal pads or via holes. This further complicates the configuration of the system board and can cause heat distribution problems according to BGA design rules. Aside from the aforesaid disadvantages, in order to obtain the bandwidth benefit from the 128-bit MD bus lines in the proposed computer system 3, a two-bank graphic memory is needed to make the 128-bit MD bus lines feasible. This also violates the trend toward low-cost computer systems and high-density memory chips. In summary, too many pin counts not only result in an unacceptable increase in chip size, but also complicate the system board space/routing.
In co-pending U.S. patent application Ser. Nos. 09/199,270 and 09/199,478, the applicant disclosed a computer system including an integrated core and graphic controller device that incorporates both core logic controller and graphic controller functions, and a system memory that is shared by both the core logic controller portion and the graphic controller portion of the integrated core and graphic controller device, thereby achieving a unified memory architecture (UMA) that results in cost savings by reducing the system board space and the components on the system board. In addition, the system board space/routing effort and the memory bus pin counts are also minimized in the disclosed computer systems. However, if the 64-bit memory data bus is replaced by a 128-bit memory data bus in the disclosed computer systems to achieve better VGA performance, the problems of increased memory pin count and increased complexity of the system board space/routing will still be encountered.
Therefore, the object of the present invention is to provide an integrated core and graphic controller device capable of accessing memory data simultaneously from a system memory pool and a separate stand-alone frame buffer memory pool, whereby the benefit of more memory access bandwidth associated with 128-bit frame buffer memory data lines can be obtained for optimum graphical performance at the lowest memory pin count and without complicating the system board space/routing.
According to the present invention, a computer system comprises an integrated core and graphic controller device including a core logic controller portion and a graphic controller portion, a system memory pool, and a stand-alone frame buffer memory pool separate from the system memory pool. A first memory data bus interconnects the integrated core and graphic controller device and the system memory pool. A second memory data bus interconnects the integrated core and graphic controller device and the frame buffer memory pool. A memory address and control signal bus interconnects the integrated core and graphic controller device, the system memory pool and the frame buffer memory pool. The graphic controller portion of the integrated core and graphic controller device is capable of generating a same set of address signals received by the system memory pool and the frame buffer memory pool via the memory address and control signal bus such that the graphic controller portion is able to access simultaneously first word part display data from the system memory pool via the first memory data bus and second word part display data from the frame buffer memory pool via the second memory data bus.